New in Release 1.2
New memory timings management/creation
Thanks to the new user interface it is now possible to create an infinite amount of different memory timings specifying the bus interface speed and the latency of each single operation performed by the memory.
New Q&A support page
Need support? No problem, with the new Q&A support page you can directly contact the SSDExplorer developers and get all the support you need to run your design.
New user data cache parameter in controller architecture module
To boost the overall performance and endurance, new SSD architectures are provided with a DRAM buffer which can be used also to cache user data. NVRAM architectures exploits this approach. With the user data cache parameter you can simulate the behavior of these new architectures.
Fix & Improvements
Improved user data storage security
We do care that your design data are secure. With the new data storage backbone, user’s data are secured by a base64 encoded password, persisted for an unlimited amount of time, and always recoverable if required.
Part of the simulation engine and the online web interface has been rewritten to avoid possible meta-conditions which could cause data misalignment and unstable simulations.
Improved simulation speed
Simulation time is everything to us. We partially rewritten the low-level simulation kernel of SSDExplorer to allow users to simulate up to 10 Million cycle-accurate transaction per day.
Improved simulation parallelization process
Simulation flexibility is mandatory. The simulation parallelization process is now able to support up to 8 independent/concurrent simulations or a single job splitted in 8 parts.
Improved workload generation
Thanks to the new workload generation and the full QEMU support, SSDExploer now supports both synthetic and real world traffics.
Change User data context - Comprehensive disk latency evaluation
Thanks to the new data processing algorithm, it is possible to perform a complete breakdown of the latency curves of the disk. For both the read and the write latency the probability density function and the cumulative distribution function are provided.
New Simulation engine - TLC memory architecture is now available
The triple-level-cell (TLC) NAND flash architecture is now available for simulation
New error recovery flow available
NAND assisted Soft-decision (NASD) is now available as error recovery flow in the firmware database.